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FIR IP

   

Features 

 

  • Multiply-Accumulate(MAC)architecture
  • Filter order 4-2048 
  • Single or multiple(up to 16) MAC engines used to achieve specified filter performance
  • Supports different input/output data throughout 
      - Single-rate filter
          - Polyphase interpolator(interpolation rate value 2-16) 
          - Polyphase decimator(decimation rate value 2-16)
  • Only signed input data and coefficient(complement code)supported,output data complement code
  • Input data precision 9-16 bit
  • Filter coefficients precision 9-16 bit
  • The IP can work well up to 100MHz(clock rate)


Block diagram

 

 

 

 

Resource and performance

 

 


Download

 

Doc(.pdf)

 

CME_FIR_user_guide(EN01)

CME_FIR_example_user_guide(EN01)

 

Design(.rar)

 

FIR_example_M5

 




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