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GPIO IP

 

Features

 

  • Configurable output_mask function
  • Support AHB interface and EMIF interface
  • 32-bit AHB data buses
  • 8-bit EMIF data buses
  • Support single AHB transfer
  • Programmable BASE_ADDR for internal registers
  • EMIF interface address must be 0x4 aligned,AHB interface address must be 0x10 aligned


Block diagram

 




Resource and performance

 

EMIF interface


AHB interface




Download

 

Doc(.pdf)

 

CME_gpio_user_guide(EN01)

CME_gpio_example_user_guide(EN01)

 


Design(.rar) 

 GPIO_example_M5&M7






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