AES IP
The AES IP accepts 8bits/16bits/32bits input data(merged to a 128-bit data in the IP)and generates a corresponding 128-bit cipher/plain text output word using a supplied 128,192 or 256-bit AES key. It supports encryption/decryption function and provides the interface that can be connected with processor or user logic in CME FPGA.
Features
Block diagram
Resource and Performance
Download
Doc(.pdf)
CME_AES_example_user_guide(EN01)
Design(.rar)