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AES IP

 

The AES IP accepts 8bits/16bits/32bits input data(merged to a 128-bit data in the IP)and generates a corresponding 128-bit cipher/plain text output word using a supplied 128,192 or 256-bit AES key. It supports encryption/decryption function and provides the interface that can be connected with processor or user logic in CME FPGA.

 

 

Features

 

  • Configurable cores provided for encryption or decrytion
  • AES key 
      - Support 128,192 or 256-bit Key Size 
      - Support dynamic cofigurable key
  • Simple external interface 
      - Support 8,16 and 32 bits interface for M5&M7 
      - Support 32 bits interface for HR3
  • Support ECB and CBC mode 
      - Support ECB and CBC mode for M5&M7 
      - Support ECB mode for HR3


Block diagram

 

 



Resource  and Performance

 

 

 

 

 

 



Download

 

Doc(.pdf)

 

CME_AES_user_guide(EN01)

CME_AES_example_user_guide(EN01)

 

 

Design(.rar)

 

AES_example_M7



 



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